1. Field of the Invention
This invention relates to a microprogram control circuit of a microprocessor, the operations of which are controlled by microcommands, and more particularly, to means for switching functions of microcommands.
2. Description of the Prior Art
FIG. 8 is a block diagram showing a prior art microprogram control circuit. Designated at 1 is microcommand storage means (hereinafter referred to as microcommand ROM), at 2 is microdata indicative of the contents of microcommands read out from the microcommand ROM 1, at 3 is a microdata register for holding microdata 2, at 4 is a decoder for decoding microdata and parameter information, at 5 is control signal obtained from the decoder 4, at 6 is microaddress data designating microcommand execution entries, at 7 is a microaddress pointer for accessing the microcommand ROM 1, at 8 is a counter for up-counting microaddress data from the micropointer 7, at 9 is next microaddress data indicative of the next microaddress with the content of address field of the microdata 2, at 10 is a next microaddress data register for storing the next microaddress data 9, at 11 is a microaddress stack register for storing return microaddress 6 when executing a sub-routine with a microcommand, at 12 is a command decoder for decoding externally fetched commands, at 13 is a decoder code obtained from the command decoder 12, at 14 is a microaddress register for holding microaddress code designating microcommand start entry address of the decoder code 13, at 15 is a microparameter register for storing parameter information such as addressing mode in the decoder code 13, and at 16 is a microparameter information.
FIG. 9 is a view showing a command format for explaining a method of microcommand start entry selection for every command in the prior art example. In the Figure, designated at 17 is a one-word command, at 18 is a two-word command, at 19 is an operation code prescribing a command operation, at 20 is a destination field designating the address of destination data and method of accessing the same address, at 21 is a size field designating the size of source data, at 22 is a source field designating the address of source data and method of accessing the same address, and at 23 is an extended field designated by the source field 22.
FIG. 10 is a view showing a horizontal microcommand entry configuration. In the Figure, designated at 24 is a microcommand, at 25 is a microaddress field designating the microaddress 6 of the next microcommand, and at 26 is a microsequence field designating the process sequence of a microprogram.
The operation of the prior art example will now be described with reference to FIGS. 8, 9 and 10. First, a method of production of the decoder code 13 will be described. A command which is fetched from an external storage unit (not shown) is supplied to the command decoder 12. The command decoder 12 generates a microaddress code corresponding to the start entry of microcommand 24 by specifying the kind of command according to the operation code 19. Simultaneously with the generation of the microaddress code, a parameter information code is generated from addressing mode for accessing destination and source data designated by the destination and source fields 20 and 22 and also from source data size information designated by the size field 21. The microaddress code and parameter information code are provided as the decoder code 13 from the command decoder 12. The microaddress code is stored in the microaddress register 14, while the parameter information code is stored in the microparameter register 15. When there are such additional information as off-set information and instantaneous value data for an addressing mode to access source data with two-word command 18 rather than one-word command 17, such information is provided as the extension field 23 designated by the source field 22. Data as to the size (which is one word in this case) of the extension field 23 and also as to whether there is the extension field 23, are provided as a source field parameter information code which also includes such data as the addressing mode and register No., i.e., as the decoder code 13. This means that the start entry of the microcommand 24 designated by the operation code 19 is not fixed in the format of the command. In other words, the start entry address of the microcommand 24 is determined by the sole operation code 19 and is independent of the contents of the source and destination fields 22 and 20, that is, if the operation code 19 indicates the same content of process, the microaddress 6 is the same with the one-word command 17 which does not have the extension field 23 and with the the two-word command 18 which has the extension field 23.
The microcommand 24 is read out in the following operation. A reading operation of the microcommand ROM 1 is started when the decoder code 13 is supplied to the microaddress register 14 and microparameter register 15. The microaddress 6 is read out from the microaddress register 14, and the microparameter information 16 is read out from the microparameter register 15. The microaddress 6 is held in the microaddress pointer 7, while the microparameter information 16 is held in the decoder 4. The. microaddress pointer 7 accesses the microcommand in the microcommand ROM 1 according to the microaddress 6 for reading the microcommand 24 as the microdata 2 into the microdata register 3.
Depending on the way of obtaining the microaddress 6, of the next microcommand 24 to be executed, designated by the microsequence field 26 thereof, different operations are executed as follows.
First, in case of a microcommand without any branch, the microdata 2 is provided from the microdata register 3 to the decoder 4. The decoder 4 decodes the previously held microparameter information 16 and microdata 2 and generates control signal 5 for controlling an arithmetic unit or the like. As soon as the microdata 2 is provided from the microdata register 3 to the microdecoder 4, the next decoder code 13 is set in the microaddress register 14 and microparameter register 15. When the microsequence field 26 of the microcommand 24 indicates the end thereof, the microaddress 6 for the execution of the next microcommand is provided from the microaddress register 14 to the microaddress pointer 7, while the microparameter information 16 is provided from the microparamter register 15 to the decoder 4, thus reading out new microcommand 24 from the ROM 1.
When a command decoded in the command decoder 12 is executed with a plurality of microcommands 24, the counter 8 up-counts the microaddress 6 of the microaddress pointer 7 concurrently with the reading of microcommand 24 from the microcommand ROM 1 until the microsequence field 26 indicates the end of the microcommand 24. The up-counted microaddress 6 is used to read out the next microcommand 24.
When the microsequence field 26 of the microcommand 24 indicates the branching thereof, i.e., when a command decoded by the command decoder 12 is executed with a plurality of microcommands 24, the microdata register 3 provides the microaddress field 25 of the microdata 2 as the next microaddress data to the next microaddress data register 10. Meanwhile, the microdata 2 that is provided by the microaddress field 25 is supplied from the microdata register 3 to the decoder 4. The decoder 4 produces control signal 5 in the manner as described above. During this time, the microaddress pointer 7 reads the microaddress 6 into the next microaddress data register 10 for the reading of the next microcommand 24 until the microsequence field 26 indicates non-branching or end of the microcommand 24.
Finally, when the microsequence field 26 of the microcommand 24 indicates sub-routine branching of microcommand 24, i.e., when the microcommand 24 is for execution of microsub-routines, more specifically, when a command decoded by the command decoder 12 is executed with microcommand 24 which is common to other commands, the microdata register 3 provides the microaddress field 25 of microdata 2 as next microaddress data for a jumped sub-routine destination to the next microaddress data register 10. Meanwhile, the microdata 2 provided by the microaddress field 25 is supplied from the microdata register 3 to the decoder 4. The decoder 4 produces control signal in the manner as described above. Concurrently, the microaddress counter 8 up-counts the microaddress 6 of the microaddress pointer 7 for storage as a microsub-routine return address in the microaddress stack register 11. The microaddress 6 of microsub-routine branch destination is read from the next microaddress data register 10 into the microaddress pointer 7 to execute a branched sub-routine. When the microsequence field 26 indicates the end of the branched microsub-routine, the microaddress pointer 7 reads the microaddress 6 of the microaddress stack register 11 as the sub-routine return destination address for the reading of the next microcommand 24.
Timings in the above operation will be briefly described with reference to FIGS. 11 to 14. Referring to FIG. 11, designated at 27 is a flow of execution of command I, at 28 is a flow of execution of command II, and at A to D are operation cycles for microcommand reading. The arrows indicate the direction of data shift. The reference numerals and symbols like those in FIG. 8 indicate the same functions.
Basically, the four cycles A to D constitute a microcommand read cycle.
First, a case when the execution of a command provided from the command decoder 12 is ended by a single microcommand will be described with reference to FIG. 11. In cycle D immediately preceding the reading of data from the ROM 1, the data code 13 of the command I is provided from the command decoder 12, and the microaddress 6 is provided to the microaddress register 14. In cycle A, the microaddress 6 is read into the microaddress pointer 7, in cycle B the ROM 1 is accessed, in cycle C the microdata 2 is read into the microdata register 3, in cycle D it is decoded together with the microparameter information 16 in the decoder 4, and in the next cycle A the control signal 5 is provided.
In the cycle D, the decoder code 13 of the command II is provided from the command decoder II to be processed in the manner as with the command I.
Now, the way of obtaining the next microaddress in case of executing a plurality of microcommands will be described. FIG. 12 shows a case of a microcommand which does not branch. In cycle C microaddresses 6 of the microaddress pointer 7 are fetched and up-counted by the counter 8 to be delivered to the microaddress pointer 7 in cycle D. In the next cycle B, the next microcommand is accessed by the micropointer 7.
FIG. 13 shows a case of a microcommand which branches. In this case, in cycle C the next microcommand address 9 indicated by the address field 25 of a microcommand provided by the microdata register 4 is stored in the next microaddress register 10. In the next cycle A it is delivered to the micropointer 7, and in the next cycle B the destination microcommand is accessed by the micropointer 7.
FIG. 14 shows a case of sub-routine branching. In this case, in cycle C the microaddresses 6 of the microaddress pointer 7 are fetched and up-counted by the counter 8, and in cycle D it is delivered to the microaddress stack register 11. In the next cycle A it is delivered to the microaddress pointer 7, and in the next cycle B the destination microcommand is accessed.
In the above prior art example, alterations of a microcommand execution procedure are possible by altering the programming of the microaddress field and microsequence field in the microcommand. This can be readily implemented by altering, in the process of manufacture, data for programming with the microcommand ROM.
However, when it is desired to add new commands or expand or alter the functions of commands, it is necessary to effect programming with an expansion microcommand ROM or the like which is additionally provided on the chip. This dictates a drastic circuitry change such as to permit decoding of the microaddresses of the new expansion microcommand ROM as command by the command decoder. This means an extension of the development time and poses problems in the development of new products with alteration of microcommands. The claimed invention solves this problem by providing circuitry which allows easy expansion and/or alteration of the functions of commands by switching those functions with extended functions.